1. Field of the Invention
The present invention relates to semiconductor memory devices including memory cell arrays in which data are read onto bit lines from memory cells and in which data are written into and refreshed in memory cells.
The present application claims priority on Japanese Patent Application No. 2008-167059, the content of which is incorporated herein by reference.
2. Description of Related Art
Various types of LSI devices incorporating dynamic random-access memories (DRAM) have been developed and disclosed in various documents such as Patent Documents 1 to 5, wherein various technologies have been developed to efficiently form smoothing capacitances and capacitances of logic circuits in small areas by use of capacitances of memory cells.                Patent Document 1: Japanese Unexamined Patent Application Publication No. 2003-332532        Patent Document 2: Japanese Unexamined Patent Application Publication No. H11-214649        Patent Document 3: Japanese Unexamined Patent Application Publication No. H05-174578        Patent Document 4: Japanese Unexamined Patent Application Publication No. 2000-348488        Patent Document 5: Japanese Unexamined Patent Application Publication No. 2005-167039        
Patent Document 1 teaches a semiconductor device in which word lines and bit lines are shared between memory cell arrays, wherein a common terminal of bit lines is supplied with a power-supply potential VDD, a common cell plate terminal is supplied with a ground potential VSS, and a common terminal of word lines is supplied with a prescribed potential higher than the power-supply potential VDD by a threshold voltage of a MOS transistor (for selecting a memory cell) or more, thus forming a smoothing capacitance between the power-supply potential VDD and the ground potential VSS by turning on the MOS transistor.
The technology of Patent Document 1 is disadvantageous in that smoothing effects decrease due to high-frequency noise occurring in the memory cell array because of the on-resistance of the MOS transistor connected in series with the smoothing capacitance. It includes an exclusive array exclusively devoted to the smoothing capacitance, which is hardly applied for the purpose of suppressing plate noise occurring between plate electrodes of the memory cell array. This is because, in the case of a large-scale DRAM, an actually operating memory cell array is normally distanced from an exclusive array devoted to the smoothing capacitance. Forming the exclusive array in addition to the memory cell array should increase the overall chip area.
Patent Document 2 teaches a consolidated semiconductor integrated circuit device in which a capacitor having the same constitution as a capacitor of a DRAM-cell is arranged in a logic circuit and is used as a smoothing capacitance or a capacitance of the logic circuit. This technology is hardly applied for the purpose of suppressing plate noise occurring in the memory cell array because the smoothing capacitance is not formed in the area of the memory cell array. This is because, in the case of a large-scale DRAM, an actually operating memory cell is normally distanced from the smoothing capacitance. Forming the smoothing capacitance in addition to the memory cell array should increase the overall chip area.
Other technologies have been developed to reduce noise of memory cell arrays by use of decoupling capacitors.
Patent Document 3 teaches a semiconductor device in which a power-supply line and a ground line for a sense amplifier of a memory cell array are formed in a comb-shape on mesh wiring, wherein they are formed in a nesting structure so as to efficiently form a decoupling capacitance between the power supply and the ground. However, this technology is hardly applicable to a decoupling capacitor formed between the cell plates because it cannot achieve a high smoothing effect due to the shortage of a wiring area.
Patent Document 4 teaches a semiconductor memory device in which electric charge is accumulated in a capacitance of a memory cell array and is used for a power supply driving a sense amplifier. This technology is capable of reducing a peak current in the power supply of the sense amplifier but is hardly applicable to a decoupling capacitor formed between the cell plates driven by a fixed power supply.
Further technologies have been developed to efficiently form decoupling capacitors by use of vacant areas of logic circuits.
Patent Document 5 teaches a semiconductor device in which a dummy gate used for the purpose of suppressing dispersions of measurements in processing is formed in a vacant area of a peripheral circuit so that the gate capacitance thereof is used as a decoupling capacitor between the power supply and the ground. However, this technology should increase parasitic resistance with the cell plates because the decoupling capacitor is formed outside the memory cell array. In other words, this technology cannot efficiently form a decoupling capacitor between the cell plates in a small area.
In the above circumstances, the present inventors have recognized that it is necessary to reduce noise occurring between the plates serving as the opposite electrodes of a capacitor when reading data onto bit lines from memory cells and when writing and refreshing data in memory cells.